Process for etching the gate in MOS technology using a SiON-based hard mask

ABSTRACT

A process for etching a gate conductor material in the fabrication of MOS transistors is presented. A hard mask layer composed of silicon oxynitride is formed upon a gate conductor layer. The hard mask layer is preferably patterned using a resin layer. The patterned hard mask layer is preferably used to form a patterned gate conductor. The gate conductor is preferably composed of polycrystalline silicon or a silicon-germanium alloy.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Generally, the invention relates to the etching of the gate material inthe fabrication of field-effect transistors.

2. Description of the Related Art

In the fabrication of MOS transistors, polysilicon or an alloy ofsilicon and germanium is generally used as the gate material. Thismaterial is deposited on a thin layer of thermal oxide, also called gateoxide, and then etched to the dimensions of the gate.

The etching, by any means whatsoever, may be carried out using a hardmask which defines the region intended subsequently to form the gate andwhich protects the said region during the operation. An inorganicmaterial, such as silicon dioxide or silicon nitride, is thereforenormally used for the hard mask. The absence of carbon in the materialof which the mask is composed, responsible for destroying the gate oxidelayer when etching the gate, makes it possible to significantly increasethe selectivity of the etching of the gate material made ofpolycrystalline silicon or of a silicon-germanium alloy with respect tothe gate oxide.

Nevertheless, the use of these conventional masks has drawbacks whichimpair the quality of the transistors fabricated.

It is known to isolate the future active regions of a semiconductordevice in a conventional manner (LOCOS) or by shallow trenches (STI orShallow Trench Isolation) using silicon dioxide. When the hard mask foretching the gate is made of silicon dioxide, its removal runs the riskof cutting away the trenches or of destroying the isolation regionbecause it is of the same nature as the isolation oxide.

Moreover, using a hard mask based on silicon nitride runs the risk ofdestroying the gate material when removing the mask. This is because theprocess of etching silicon nitride is very similar to that for silicon,which results in poor etching selectivity between these 2 materials andin detection of the end of etching of the hard mask that occurs at thegate not being sufficient to prevent partial destruction of the gatelying beneath the hard mask.

It would therefore seem to be necessary to develop a process for etchingthe gate material which does not have the abovementioned drawbacks.

SUMMARY OF THE INVENTION

The inventors have demonstrated that the use of a thin and porous layerbased on nitrided silicon oxide SiON, as a hard mask for etching thegate material, makes it possible to overcome the drawbacks observed withthe masks of the prior art. The material SiON has all the propertiesrequired of a hard mask. Furthermore, its removal is simplified, withoutin any way destroying either the thermal oxide or the gate material.

In the microelectronics field, nitrided silicon oxide is generally usedas material for antireflective layers. In particular, this materiallimits the reflectivity of tungsten- or aluminium-based subjacent layersduring the photolithography of these layers, as well as the parasiticeffects of reflection off the subjacent layers during exposure of thephotosensitive organic layer.

The invention provides a process for etching the gate material in thefabrication of field-effect transistors, comprising at least thefollowing steps:

a) a thin and porous layer of a SiON-based alloy is deposited on asemiconductor substrate coated with a thermal oxide first layer and witha second layer made of polycrystalline silicon or of a silicon-germaniumalloy;

b) the said layer is etched using a resin mask produced on theSiON-based layer, in order to form a hard mask;

c) after the masking resin has been removed, the region predefined bythe hard mask in the layer made of polycrystalline silicon or of asilicon-germanium alloy is etched in order to form the future gate; and

d) the SiON-based hard mask is removed.

In step a), “thin layer” should be understood to mean a layer whosethickness is between 500 and 2000 Å, typically 1500 Å. The compositionof the alloy of which this layer is composed is preferablySi_(x)O_(y)N_(z), in which x is between 35 and 45% and z is between 40and 60%, y making the total up to 100%. These percentages are atomicpercentages.

The SiON-based alloy layer may be deposited on the gate material byplasma-enhanced chemical vapour deposition at low temperature, and moreparticularly at about 300° C.

The etching of the SiON-based hard mask in step b) is advantageouslyassisted by end-of-etching detection that takes place at the subjacentlayer based on polycrystalline silicon or on a silicon-germanium alloythen acting as a stop layer for the operation.

In step c), the etching of the gate in the layer based onpolycrystalline silicon or on a silicon-germanium alloy may also beadvantageously assisted by end-of-etching detection that takes place atthe thermal oxide layer acting as the stop layer for the operation.

In step d), the SiON-based hard mask may be removed chemically, such asespecially by liquid etching, or by plasma etching. This operation mayadvantageously be assisted by end-of-etching detection that occurs asthe future gate then acting as a stop layer for the operation.

Alternatively, in step d), the removal of the SiON-based hard mask ispreceded by a step of forming lateral spacers based on silicon dioxideor on silicon nitride which are placed on each side of the future gate.

BRIEF DESCRIPTION OF THE DRAWINGS

Other advantages and characteristics will appear upon examination of thedetailed description of entirely non-limiting ways of implementing andof carrying out the invention, and of the appended drawings, in which:

FIGS. 1 a to 1 e and 1 e′ illustrate the way of implementing the processof the invention.

DETAILED DESCRIPTION OF THE INVENTION

As illustrated in FIG. 1 a, a thin and porous layer 4 of an SiON-basedalloy is deposited on a semiconductor substrate 1 coated in successionwith a thermal oxide layer 2 and with a layer of a gate material. Thethermal oxide layer 2 generally consists of silicon dioxide andtypically has a thickness of between 30 and 250 Å. The gate material isbased on polycrystalline silicon or on a silicon-germanium alloy and hasa thickness of between 1000 and 4000 Å, typically 2000 Å.

The SiON-based layer is deposited by low-temperature plasma-enhancedchemical vapour deposition (PECVD). Temperatures of about 300° C. willtypically be used. This type of deposition has the advantage overhigh-temperature furnace deposition of using only a low heat balance.During high-temperature oven deposition, dopant diffusion is observedwhen deposition takes place on materials already doped. With thelow-temperature PECVD deposition according to the invention, dopantdiffusion into the materials is reduced or even eliminated.

The other conditions for eliminating the PECVD deposition process arethose usually employed in the microelectronics field. In the usualmanner, it is preferred to operate with an inert gas, for examplenitrogen, argon or helium. The active gas mixture contains precursors ofthe constituent elements of the SiON-based alloy. The composition of thealloy is Si_(x)O_(y)N_(z), in which x is between 35 and 45%, z isbetween 40 and 60% and y makes the total up to 100%. These percentagesare atomic percentages.

By varying the gas mixture during deposition, the composition of theSiON-based layer may be modified.

By adjusting the proportion of nitrogen in the alloy and the temperatureconditions during deposition, it is possible to vary the selectivity,especially during removal of the mask, with respect to silicon dioxide,by using a high atomic percentage of nitrogen, or with respect tosilicon nitride, by decreasing the proportion of nitrogen. It is thuspossible, by adjusting the gas mixture, to optimize the selectivity ofthe etching of the mask with respect to the other materials present andexposed.

A thin and porous SiON-based layer, labelled 4 in FIG. 1 a, is thusdeposited with a thickness of between 500 and 2000 Å, typically 1500 Å,on the layer 3 of gate material.

As illustrated in FIG. 1 b, a photosensitive masking resin was depositedon the thin and porous SiON-based layer and etched, for example byphotolithographic etching, using a mask that reproduces the regionintended subsequently to form the gate. Using this resin mask 5, thethin and porous SiON-based layer 4 is etched by dry anisotropic etchingin order to form the hard mask, also labelled 4.

This step of etching the hard mask is advantageously assisted byend-of-etching detection that takes place at the layer 3 made ofpolycrystalline silicon or of a silicon-germanium alloy then acting asthe stop layer. The etching takes place and the end-of-etching detectionoccurs under conditions usual in the microelectronics field.

After the hard mask 4 has been etched, the masking resin is removed inthe usual manner. The device illustrated in FIG. 1 c is obtained, inwhich the semiconductor substrate 1 is covered with a thermal oxidefirst layer 2 and with a second layer 3 based on polycrystalline siliconor on a silicon-germanium alloy. The latter layer lies beneath a hardmask 4 based on an SiON alloy predefining the region intended to formthe gate.

As illustrated in FIG. 1 d, the layer 3 is etched in a conventionalmanner by dry anisotropic etching using the SiON-based hard mask 4 inorder to form the future gate of the MOS transistor. The etching of thegate material may advantageously be assisted by end-of-etching detectionthat takes place at the thermal oxide layer 2 then acting as the stoplayer for the etching operation.

The process has an additional advantage in this step of etching the gatein that the SiON material used as hard mask has antireflectiveproperties which limit reflection off the subjacent layer when thelatter is etched by photolithographic etching.

In a final step, the SiON-based hard mask 4 is removed in a simplifiedmanner. This removal preferably takes place by chemical means,especially by liquid isotropic etching, or by plasma etching. It turnsout in fact that removal by chemical means does not destroy the exposedthermal oxide layer 2 since the etching rate of the SiON-based materialmay be up to one hundred and fifty times greater than that of silicondioxide and seven times that of silicon nitride in liquid etching andforty times that of silicon dioxide in plasmic etching. Furthermore, theselectivity of this removal operation is infinite with respect to thepolycrystalline silicon or to the silicon-germanium alloy of which thegate material is composed. This infinite difference between the etchingrates of the SiON-based material and the gate material advantageousassists the step of removing the hard mask 4 by end-of-etching detectionthat takes place at the layer 3 forming the gate and then acting as thestop layer for the etching. The etching conditions and theend-of-etching detection conditions are the usual ones in themicroelectronics field.

The high selectivity during removal of the mask for etching theSiON-based material with respect to the materials surrounding it mayalso advantageously be used when removing the hard mask after lateralspacers based on silicon dioxide or on silicon nitride have been formed.Thus, according to one method the step of removing the SiON-based hardmask is preceded by a step of forming lateral spacers 6 based on silicondioxide or on silicon nitride which are placed on each side of thefuture gate 3. It is thus possible, after removing the hard mask, toobtain spacers 6 whose height is greater than the gate height byapproximately the value of the thickness of the SiON layer. This type ofspacer is beneficial, especially in order to limit the short-circuitphenomena observed between the gate and the active region duringselective siliciding of the silicon.

Thus, according to the method the devices illustrated in FIGS. 1 e and 1e′ are obtained.

In FIG. 1 e, the semiconductor substrate 1 is coated over its entiresurface with a thermal oxide 2 on which the layer 3 based onpolycrystalline silicon or on a silicon-germanium alloy forms the futuregate of a MOS transistor.

In FIG. 1 e′, the semiconductor substrate 1 is coated over its entiresurface with a thermal oxide 2 on which spacers 6 made of silicondioxide or of silicon nitride are placed on each side of the future gate3 based on polycrystalline silicon or on a silicon-germanium alloy. Theheight of these spacers is greater than the height of the gate byapproximately the thickness of the SiON-based hard mask.

The semiconductor device thus obtained may undergo the usual subsequenttreatments necessary for the fabrication of an MOS transistor.

Further modifications and alternative embodiments of various aspects ofthe invention will be apparent to those skilled in the art in view ofthis description. Accordingly, this description is to be construed asillustrative only and is for the purpose of teaching those skilled inthe art the general manner of carrying out the invention. It is to beunderstood that the forms of the invention shown and described hereinare to be taken as the presently preferred embodiments. Elements andmaterials may be substituted for those illustrated and described herein,parts and processes may be reversed, and certain features of theinvention may be utilized independently, all as would be apparent to oneskilled in the art after having the benefit of this description of theinvention. Changes may be made in the elements described herein withoutdeparting from the spirit and scope of the invention as described in thefollowing claims.

We claim:
 1. Process for etching a gate material in the fabrication ofMOS transistors, comprising: a) a thin and porous layer of a SiON-basedalloy whose composition is Si_(x)O_(y)N_(z), in which x is between about0.35 and 0.45 and z is between about 0.40 and 0.60, y differing fromzero and making the total of x+y+z up to 1, is deposited on asemiconductor substrate already coated with a thermal oxide first layerand with a second layer comprising polycrystalline silicon; b) the saidSiON-based layer is etched, using a resin mask produced on theSiON-based layer, in order to form a hard mask; c) after the maskingresin has been removed, the region predefined by the hard mask in thelayer based on polycrystalline silicon or on a silicon-germanium alloyis etched in order to form the future gate; and d) the SiON-based layeris removed.
 2. Process according to claim 1, wherein in step a), thethin and porous layer of a SiON-based alloy has a thickness of betweenabout 500 and 2000 Å.
 3. Process according to claim 1, wherein the thinand porous SiON-based layer is deposited by low-temperatureplasma-enhanced chemical vapour deposition.
 4. Process according toclaim 1 wherein in step b), the etching of the hard mask is assisted byend-of-etching detection that takes place at the second layer. 5.Process according to claim 1 wherein in step c), the etching of the gatein the second layer is assisted by end-of-etching detection that takesplace at the thermal oxide layer.
 6. Process according to claim 1wherein the SiON-based hard mask is removed by liquid isotropic etchingin step d).
 7. Process according to claim 1 wherein the SiON-based hardmask is removed by plasma etching in step d).
 8. Process according toclaim 6 wherein the etching is assisted by end-of-etching detection thattakes place at the second layer.
 9. Process according to claim 1 whereinin step d), the removal of the SiON-based hard mask is preceded by astep of forming lateral spacers based on silicon dioxide which areplaced on each side of the future gate.
 10. Process according to claim7, wherein the etching is assisted by end-of-etching detection thattakes place at the second layer.
 11. Process according to claim 1wherein in step d), the removal of the SiON-based hard mask is precededby a step of forming lateral spacers based on silicon nitride which areplaced on each side of the future gate.
 12. A process for etching a gatematerial in the fabrication of MOS transistors, comprising: forming anoxide layer upon a semiconductor substrate; forming a gate conductorlayer upon the oxide layer, the gate conductor layer comprising asilicon-germanium alloy; forming a hard mask layer upon the gateconductor layer, the hard mask layer comprising an alloy whosecomposition is Si_(x)O_(y)N_(z) where x is between about 0.35 and 0.45,z is between about 0.40 and 0.60, and y is greater than zero and whereinthe total of x+y+z is about 1.0; forming a patterned resin masking layerupon the hard mask layer; etching the hard mask layer using thepatterned resin mask such that the hard mask layer is patterned;removing portions of the gate conductor layer exterior to the patternedhard mask layer to form a gate conductor.
 13. The process of claim 12,wherein the hard mask layer is formed by a low-temperatureplasma-enhanced chemical vapour deposition.
 14. The process of claim 12,wherein etching the hard mask layer comprises ending the etching of thehard mask layer the gate conductor layer is detected.
 15. The process ofclaim 12, wherein removing potions of the gate conductor layer comprisesending the removal of the gate conductor layer when the thermal oxidelayer is detected.
 16. The process of clam 12, wherein etching the hardmask layer comprises liquid isotropic etching.
 17. The process of claim12, wherein etching the hard mask layer comprises plasma etching. 18.The process of claim 12, further comprising removing the hard masklayer.
 19. An integrated circuit prepared using the process of claim 12.20. An integrated circuit comprising: a gate oxide layer formed upon asemiconductor substrate; a gate conductor formed upon the gate oxidelayer, the gate conductor comprising a silicon-germanium alloy orpolycrystalline silicon; and a hard mask layer formed upon the gateconductor, the hard mask layer comprising an alloy whose composition isSi_(x)O_(y)N_(z) where x is between about 0.35 and 0.45, z is betweenabout 0.40 and 0.60, and y is greater than zero and wherein the total ofx+y+z is about 1.0.